Optional PLL configuration for BOOTSEL mode. (ECC)
This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output.
If no configuration is given, the crystal is assumed to be 12 MHz.
The PLL frequency can be calculated as:
PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2)
Conversely the crystal frequency can be calculated as:
XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV
(Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.)
Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed.
| FBDIV | PLL feedback divisor, in the range 16…320 inclusive. |
| POSTDIV1 | PLL post-divide 1 divisor, in the range 1…7 inclusive. |
| POSTDIV2 | PLL post-divide 2 divisor, in the range 1…7 inclusive. |
| REFDIV | PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) |